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NBXDPA012 2.5 V / 3.3 V, 106.25 MHz / 212.5 MHz LVDS Clock Oscillator
The NBXDPA012 dual frequency crystal oscillator (XO) is designed to meet today's requirements for 2.5 V and 3.3 V LVDS clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable 106.25 MHz or 212.5 MHz, ultra low jitter and phase noise LVDS differential output. This device is a member of ON Semiconductor's PureEdget clock family that provides accurate and precision clock solutions. Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape and reel in quantities of 1000.
Features http://onsemi.com MARKING DIAGRAM
NBXDPA012 106.25/212.5 AWLYYWW
6 PIN CLCC LN SUFFIX CASE 848AB NBXDPA012 106.25/212.5 A WL YY WW G or G
* * * * * * * * *
LVDS Differential Output Uses High Q Fundamental Mode Crystal and PLL Multiplier Ultra Low Jitter and Phase Noise - 0.4 ps (12 kHz - 20 MHz) Selectable Output Frequency - 106.25 MHz (default) / 212.5 MHz Hermetically Sealed Ceramic SMD Package RoHS Compliant Operating Range: 2.5 V 5% Operating Range: 3.3 V 10% Total Frequency Stability - $50 ppm This is a Pb-Free Device
= NBXDPA012 (50 PPM) = Output Frequency (MHz) = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
Device NBXDPA012LN1TAG NBXDPA012LNHTAG Package CLCC-6 (Pb-Free) CLCC-6 (Pb-Free) Shipping 1000/ Tape & Reel 100/ Tape & Reel
Applications
* 1x and 2x Fiber Channel * Host Bus Adapter
VDD 6 CLK CLK 54
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Crystal
PLL Clock Multiplier
1 OE
2 FSEL
3 GND
Figure 1. Simplified Logic Diagram
(c) Semiconductor Components Industries, LLC, 2009
August, 2009 - Rev. 0
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Publication Order Number: NBXDPA012/D
NBXDPA012
OE FSEL GND 1 2 3 6 5 4 VDD CLK CLK
Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 Symbol OE I/O LVTTL/LVCMOS Control Input LVTTL/LVCMOS Control Input Power Supply LVDS Output LVDS Output Description Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2.
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FSEL GND CLK CLK VDD Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output Frequency Select pin description Table 3. Ground 0 V Non-Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across differential pair. Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across differential pair. Positive power supply voltage. Voltage should not exceed 2.5 V 5% or 3.3 V 10%. Power Supply
Table 2. OUTPUT ENABLE TRI-STATE FUNCTION
OE Pin Open HIGH Level LOW Level Output Pins Active Active High Z
Table 3. OUTPUT FREQUENCY SELECT
FSEL Pin Open (pin will float high) HIGH Level LOW Level
Output Frequency (MHz) 106.25 106.25 212.5
Table 4. ATTRIBUTES
Characteristic Input Default State Resistor ESD Protection Human Body Model Machine Model Value 170 kW 2 kV 200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol VDD Iout TA Tstg Tsol Parameter Positive Power Supply LVDS Output Current Operating Temperature Range Storage Temperature Range Wave Solder See Figure 6 Condition 1 GND = 0 V Continuous Surge Condition 2 Rating 4.6 25 50 -40 to +85 -55 to +120 260 Units V mA C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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Table 6. DC CHARACTERISTICS (VDD = 2.5 V 5% or VDD = 3.3 V 10%, GND = 0 V, TA = -40C to +85C) (Note 2)
Symbol IDD VIH VIL IIH IIL DVOD Characteristic Power Supply Current OE and FSEL Input HIGH Voltage OE and FSEL Input LOW Voltage Input HIGH Current Input LOW Current OE FSEL OE FSEL 2000 GND - 300 -100 -100 -100 -100 0 1 Conditions Min. Typ. 85 Max. 105 VDD 800 +100 +100 +100 +100 25 Units mA mV mV mA mA mV
Change in Magnitude of VOD for Complementary Output States (Note 3) Offset Voltage Change in Magnitude of VOS for Complementary Output States (Note 3) Output HIGH Voltage Output LOW Voltage Differential Output Voltage VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V
VOS DVOS
1125 0 1
1375 25
mV mV
VOH VOL VOD
1425 900 250 1075
1600
mV mV
450
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 5. 3. Parameter guaranteed by design verification not tested in production.
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NBXDPA012
Table 7. AC CHARACTERISTICS (VDD = 2.5 V 5% or VDD = 3.3 V 10%, GND = 0 V, TA = -40C to +85C) (Note 4)
Symbol fCLKOUT Df FNOISE Characteristic Output Clock Frequency Frequency Stability - NBXDPA012 Phase-Noise Performance fCLKout = 106.25 MHz/212.5 MHz (See Figures 3 and 4) Conditions FSEL = HIGH FSEL = LOW (Note 5) 100 Hz of Carrier 1 kHz of Carrier 10 kHz of Carrier 100 kHz of Carrier 1 MHz of Carrier 10 MHz of Carrier tjit(F) tjitter RMS Phase Jitter Cycle to Cycle, RMS Cycle to Cycle, Peak-to-Peak Period, RMS Period, Peak-to-Peak tOE/OD tDUTY_CYCLE tR tF tstart Output Enable/Disable Time Output Clock Duty Cycle (Measured at Cross Point) Output Rise Time (20% and 80%) Output Fall Time (80% and 20%) Start-up Time Aging 1st Year Every Year After 1st 48 50 115 115 1 12 kHz to 20 MHz 1000 Cycles 1000 Cycles 10,000 Cycles 10,000 Cycles -112/-105 -123/-116 -131/-124 -131/-124 -139/-133 -161/-158 0.4 3 7 2 10 0.75 8 35 4 20 200 52 400 400 5 3 1 Min. Typ. 106.25 212.5 50 ppm dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ps ps ps ps ps ns % ps ps ms ppm ppm Max. Units MHz
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 5. 5. Parameter guarantees 10 years of aging. Includes initial stability at 25C, shock, vibration and first year aging.
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Figure 3. Typical Phase Noise Plot at 106.25 MHz
Figure 4. Typical Phase Noise Plot at 212.5 MHz
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Table 8. RELIABILITY COMPLIANCE
Parameter Shock Mechanical Mechanical Mechanical Mechanical Mechanical Standard Method MIL-STD-833, Method 2002, Condition B MIL-STD-833, Method 2003
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Solderability Vibration MIL-STD-833, Method 2007, Condition A MIL-STD-202, Method 215 Solvent Resistance Resistance to Soldering Heat Thermal Shock MIL-STD-203, Method 210, Condition I or J MIL-STD-833, Method 1001, Condition A MIL-STD-833, Method 1004 Environment Environment Moisture Resistance NBXDPA012 CLK Driver Device CLK Zo = 50 W Zo = 50 W 100 W D D Receiver Device
Figure 5. Typical Termination for Output Driver and Device Evaluation
Temperature (C) 260 217
temp. 260C 20 - 40 sec. max. peak 3C/sec. max. ramp-up
6C/sec. max.
cooling
175 150
pre-heat reflow 60180 sec. 60150 sec. Time
Figure 6. Recommended Reflow Soldering Profile
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NBXDPA012
PACKAGE DIMENSIONS
6 PIN CLCC, 7x5, 2.54P CASE 848AB-01 ISSUE C
D
4X
A
0.15 C
D1
B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. DIM A A1 A2 A3 b D D1 D2 D3 E E1 E2 E3 e H L R SEATING PLANE MIN 1.70 0.08 1.30 6.17 6.66 4.37 4.65 MILLIMETERS NOM MAX 1.80 1.90 0.70 REF 0.36 REF 0.10 0.12 1.40 1.50 7.00 BSC 6.20 6.23 6.81 6.96 5.08 BSC 5.00 BSC 4.40 4.43 4.80 4.95 3.49 BSC 2.54 BSC 1.80 REF 1.27 1.37 0.70 REF
TERMINAL 1 INDICATOR
E2
H E1
E
D2 TOP VIEW A3 0.10 C A A1 SIDE VIEW D3
1 2 3
A2
1.17
C
SOLDERING FOOTPRINT*
e
R
E3
1.50
6X
5.06
0.10 C A B 0.05 C
6X
b
6
5
4 6X
L 2.54 PITCH 1.50
DIMENSION: MILLIMETERS 6X
BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
PureEdge is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NBXDPA012/D

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